Dr. Ratul Kumar Baruah
Ph.D. Indian Institute of Technology Guwahati, India                                                                    
Designation: Assistant Professor    

Contact Details

Contact Address: Room No. 118, ECE Department, Tezpur University, Tezpur-784028, INDIA.
Phone: +91-3712-275265 (O)
Fax: +91-3712-267005/6
Email: ratulkr[AT*]tezu.ernet.in

Research Areas
  • Nanoelectronic Devices
  • VLSI Circuit Design & Layout 
  • Reliability of Electronic Devices
    • Courses
  • EL521-Design and Technology of Electronics Devices  (Current)
  • EL538-Advanced Electronic Devices 
  • EL531-Design of Digital Systems 
  • EL308-VLSI Design  
  • EL208-Engineering Electromagnetics
  • EL202-Electrical Technology
  • EL102-Basic Electronics
    • Work/Research Experience
  • Assistant Professor, Department of ECE, Tezpur University since 2009 
  • Visiting Fellow, Nanoelectronics Computation Lab, IIT Bombay under DST-FIST-NER fellowship during June 7-July15, 2011
  • Senior Research Fellow, Nano Scale Device Research Laboratory, Institute of Science, Bangalore during 2008-2009
  • Project Staff, VLSI Circuit Design Centre, Semi-Conductor Laboratory (SCL), ISRO during 2006-2007
    • Research Projects
  • Principal Investigator, DST-SERC FAST TRACK Project on VLSI Device Area, 2013-2016
  • Principal Investigator, Start up research grant on VLSI Device area, Tezpur University, 2011-2013
    •         Membership/Reviewer

  • Member, IEEE

  • Reviewer of IEEE Transactions on Electron Devices

    • Reviewer of IEEE Transactions on Nanotechnology

    • Reviewer of Nanoscience & Nanotechnology-Asia

    • Reviewer of many National & Internationl Conferences

      • Three Selected Recent Publications
          1. Ratul Kr. Baruah, Roy P. Paily, "A Dual-Material Gate Junctionless Transistor using high-k spacer for Enhanced Analog Performance", IEEE Transactions on Electron Devices, vol 61, no. 1, pp. 123–128, 2014.
          2. Ratul Kr. Baruah, Roy P. Paily, “Impact of High-k Spacer on Device Performance of a Junctionless Double-Gate Transistor”, Journal of Computational Electronics, Springer, vol. 12, no. 1, pp. 14–19, 2013.
          3. Ratul Kr. Baruah, Santanu.Mahapatra, "Justifying threshold voltage definition for undoped body transistors through crossover point concept", Physica B: Condensed Matter, Elsevier, vol. 404, no.5, pp. 1029-1032, 2009.